A high-level approach to power estimation of digital circuits at an ac- curacy of transistor-level simulation

This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation methods.